1. Field of the Invention
The present invention relates generally to a chip scale package and a method for manufacturing it. More particularly, the present invention relates to a semiconductor chip package having column leads, the column leads being electrically connected to a respective one of a corresponding set of bonding pads on a chip and extending outward from the package body. The present invention also relates to a lead frame for manufacturing the package, and to a manufacturing method thereof.
2. Background of the Related Art
As semiconductor chips have become more highly integrated and the number of input/output pads per chip has increased, the need for smaller semiconductor chip packages has also increased. Accordingly, various packaging technologies have been developed to address this need. For example, COB (chip on board) or flip chip technology allows a direct mounting of the chip onto a printed circuit board (PCB).
However, since the chip is mounted onto the PCB without carrying out reliability tests such as a bum-in test, the electronic systems into which the PCB is installed can have a defective chip. This is a drawback of these packaging technologies, because any defective chip must be repaired or replaced with a good one, after only a short period of use, and only with difficulty.
Accordingly, there still is a need to assure reliability of the package while minimizing package size to almost the same size as the chip itself. Recently, a chip-scale package (CSP) has been developed to address this need. The CSP provides advantages in that it is supplied to the end users as a known good die and can be mounted onto the PCB by employing conventional surface mount technology, allowing miniaturization and multi-functionalization of electronic systems, while retaining a size as small as a bare chip.
Nevertheless, the cost of manufacturing the CSP is relatively high, both for purchasing new equipment for production thereof, and for fabrication of individual packages.